Method and Apparatus for Capacitance Multiplication Within a Phase-Locked Loop

Introduction

Both level-one and level-two caches are highly underutilized, containing mostly dead data that will never again be used before being thrown out of the cache. This low utilization results in unnecessary power, energy, and area overheads, while also being a lost opportunity for higher performance if caches were better utilized. The proposed invention increases the utilization of the cache, enabling more live blocks to be stored in them at any given time, reducing cache misses and increasing performance.

Benefits

• A chip area of approximately 100 µm by 100 µm can realize two 50 pF physical capacitors that can be multiplied to make two capacitors with an apparent capacitance of 10 nF each. Without the invention it would take an area of about 2 square mm to realize the capacitors. The invention reduces the area by a factor of about 200.

Market Potential/Applications

"Clean-up" phase-locked loops, low bandwidth analog filters.

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University of Texas,
Austin, USA
Website : www.otc.utexas.edu