Description

A great challenge facing CMOS is power consumption. Increased energy efficiency is not only important for its own sake but also to allow continued transistor scaling and an associated increase in computational power. As device densities increase, the power used by each transistor must decrease to prevent circuit overheating.

For many years, this per-device power reduction has been accomplished in large part through reduction in power supply voltages. But there is a limit to such voltage scaling. Switching is not entirely abrupt in MOSFETs, the transistor used in CMOS. OFF-state leakage currents and associated steady-state power consumption actually increase with reductions in power supply voltages, and thus threshold voltages, due to "thermionic emission," a basic physical mechanism of transport in MOSFETs. This steady-state power consumption leads to an approximately 0.5 V "end of the roadmap" voltage limit for CMOS. Thus, there is scope in the market for technologies that provide more abrupt switching mechanisms than physically possible in MOSFETs.

Gate-voltage-controlled inter-band (Zener) tunneling is one such alternative switching mechanism not directly subject to thermionic emission. These devices have typically employed homo-barriers, with tunnel barrier shape determined by electrostatics governed by doping and gate geometry. However, to date, ON state currents have been unacceptably low and/or switching characteristics have lagged CMOS.

This proposed technology is different from others in that it incorporates, specifically, stepped or graded "type II" to "type III" heterojunction barriers to interband tunneling defined during semiconductor crystal growth. The resulting additional control over the tunnel barrier may allow more abrupt switching while not significantly compromising the ON-state leakage current.

Benefits

• Acceptable ON-OFF ratios over smaller voltage ranges than available with MOSFETs.
  
• Operation over smaller voltage ranges provides energy efficiency (as consumes less power).
  
• The associated reduction in heating allows greater device density and thus increases the computational power of CMOS like logic circuits.
  

Features

• Stepped or graded type II to type III heterojunction tunnel barriers

Market Potential/Applications

• Low-power logic and memory devices. In general, HetFETs could be used in most devices that use MOSFETs.
  

For further information please contact:

University of Texas,
Austin, USA
Website : www.otc.utexas.edu