A Method and Apparatus for Supporting Structural Hazards Using On-Chip Networks

Introduction

On chip networks are emerging as a key technology for transporting data among processing elements within a single chip. Micronetworks are networks that exist within a collection of on-chip hardware acting as a single processor. To date, micronetworks have been used to transport cache lines or inter-ALU operands (the latter in the RAW and TRIPS processors), and have been designed to handle contention, using wormhole-routed flow control.

To date, however, micronetworks have not incorporated classic flow control techniques to handle the case where receiving buffers are full, since the designs incorporating micronetworks to date do not connect structures that could overflow. However, in future processors, it may be possible to shrink many structures in the processor, resulting in lower area and power, provided that a low-overhead way to handle overflows of those reduced structures is provided.

Benefits:

• The structures can be made significantly smaller, or partitioned to a finer degree, since the cost of overflows/exceeded capacity is significantly reduced.
  
• This invention may be a necessary capability to finely partition future designs, which may be necessary for providing the sort of adaptive/flexible behavior that may be necessary to achieve extremely power-efficient execution on future designs for a wide range of application.
  

Market Potential/Applications: High-performance, low-power data processing systems

Contact:

University of Texas,
Austin, USA
Website : www.otc.utexas.edu