Introduction

On-chip networks are emerging as a key technology for transporting data among processing elements within a single chip. Power, area, and latency are all critical aspects of these on-chip networks that must be optimized together. These networks are typically organized as low-dimensional routed networks, which can route point-to-point messages quite efficiently. However, when a message must be routed to a fraction (including all) of the possible recipients on a chip, standard on-chip networks are inefficient.

Benefits:

• Allows a message to be widely sent, despite the restrictions of the on-chip network topology, by only using each network link at most once
  
• Improves power efficiency and performance at a small cost in additional hardware complexity
  

Features

Applies multicast technology to new applications limited to on-chip networks with their restricted topologies

Market Potential/Applications:

High-performance, low-power data processing systems

Contact:

University of Texas,
Austin, USA
Website : www.otc.utexas.edu